Verilog vhdltrabajos
Soy un estudiante de ingeniería electrónica que necesita aprender VHDL, XILINX y dsp. Busco alguien que pueda crear un conjunto de tutoriales en vídeo, audio y texto para ayudarme a debugear y escribir código. Estoy buscando tutoriales y clases para diseccionar y detallar algunas aspectos de un proyecto Estoy ansioso por encontrar alguien para ayudarme a que logre mis metas de aprender estás herramientas y que me sienta a gusto cuando they llegue la hora de aplicarlo.
Proyecto en xilinx empleando VHDL, clases y verificación de códigos
Implementar, simular FFT en entorno xilinx o alguna plataforma similar , bajo la plataforma Atlys Spartan-6. Simular e implementar FFT en dicha plataforma, desarrollar código VHDL y detallar minuciosamente paso a paso, tomar captures y realizar documento de word detallando cada paso la oferta es de 90 usdt. Se cuenta con la tarjeta en físico por lo cual se ofrece conexión remota, ante cualquier duda estoy abierto a conversar
A partir del codigo de cisfrado, que facilito. Implementar el codigo para descifrado. Para ello se Implementará el algoritmo de descifrado y comprobarás su funcionamiento usando el mensaje cifrado como entrada y la clave operativa (MSBF). Si la simulación es correcta, el resultado será un bloque de 64 bits a cero (u ocho bytes a cero). A continuación, descrifrarás el mensaje cifrado que faciltaré con la clave operativa asociada. Y colocarás el mensaje en claro en la caja de texto de la tarea. Se proporcionará todos los archivos, claves en privado. Se necesita para el día 2 de Noviembre, es una tarea de estudios, fácil. El tiempo estimado de trabajo es 30 min porque el codigo de cisfrado lo tengo, solo es modif...
Buenas! Veréis tengo que hacer el TFG, tengo casi hecho el código en VHDL, pero yo creo XILINX me vacila. Tengo que entregarlo antes de diciembre y necesito que alguien me lo consiga a hacer porque yo solo no lo saco. Adjunto las entidades que tengo hechas, esta casi todo ya escrito solo me falta que me funcione, que no se por que, pero no me funciona.
Requiero un contador / cronometro que pueda contar de 0 a 99.9 segs, se debera entregar codigo fuente en VHDL / Vivado asi como resultado de simulaciones
Hola Miguel Angel, dominas VHDL? Si es así creo este proyecto para hablar contigo más ya que tengo un requerimiento pequeñito para resolver. Seguimos hablando por aquí.
Hola Jorge Eduardo, como estamos? Dominas VHDL? Necesito un poco de ayuda con un pequeño proyecto. Seguimos hablando por aquí.
Hi Jorge Luis, necesito ayuda con una cuestión de VHDL bastante sencilla si fuera posible. hablame por aquí y concretamos. es un poco urgente
Implemente un sistema de ecualización en tiempo real de tres bandas (bajos, medios y altos) en el FPGA de xilixn. Desarrolle los tres filtros necesarios para el ecualizador, los puede establecer en matlab o labview. Una vez definidos los coeficientes del filtro impleméntelos en el FPGA (a través de Matlab, Laview o Multisim). Se establece un bonus de 4 puntos para el grupo que lo implemente en código VHDL.
Proyecto enfocado al diseño VHDL sobre FPGAS. Desarrollo de código y de bancos de pruebas, verificación del funcionamiento y resolución de algunas cuestiones. Tiene que estar terminado para el día 17 de diciembre. Se adjunta toda la descripción de lo que hay que hacer, así como unas plantillas para las soluciones y algunos bancos de pruebas.
El objetivo general del presente proyecto consiste en la realización, verificación funcional y validación experimental de un microcontrolador sencillo basado en un subconjunto de la arquitectura del juego de instrucciones del RISC-V. El microcontrolador debe ser descrito en SystemVerilog de modo que sea sintetizable y pueda ser implementado en una FPGA Cyclone IV de Altera. Su validación experimental se realizará en el laboratorio mediante una aplicación sencilla propuesta por cada grupo que haga uso de los recursos hardware disponibles en el módulo de test. El proyecto abarca por tanto los aspectos de verificación funcional, descripción de hardware empleando SystemVerilog, implementación de un sistema digital integrado ...
El objetivo general del presente proyecto consiste en la realización, verificación funcional y validación experimental de un microcontrolador sencillo basado en un subconjunto de la arquitectura del juego de instrucciones del RISC-V. El microcontrolador debe ser descrito en SystemVerilog de modo que sea sintetizable y pueda ser implementado en una FPGA Cyclone IV de Altera. Su validación experimental se realizará en el laboratorio mediante una aplicación sencilla propuesta por cada grupo que haga uso de los recursos hardware disponibles en el módulo de test. El proyecto abarca por tanto los aspectos de verificación funcional, descripción de hardware empleando SystemVerilog, implementación de un sistema digital integrado ...
Necesito hacer un programa en VHDL de un reloj (formato 24hs), con cronometro y con alarma. Cuando cambio a cada uno. no se debe perder la cuenta de la hora, cronometro o la alarma seteada. El reloj, la alarma y el cronometro se debe poder cargar/modificar manualmente. Detención y reinicio del cronometro. Cuando la hora del alarma coincida con el clock, prender los (o algún) led. Se deberá implementar algún tipo de barrido multiplexado para el uso de los 4 dígitos “7 segmentos”.
necesito transmitir datos numericos entre la fpga nexys 3 y el pc, usando protocolo uart por medio del puerto serial uart, comunicacion asincrona, el proyecto requiere que se lea un numero en binario tomado desde los switchs que trae la tarjeta y muestre el valor ingresado en form...fpga nexys 3 y el pc, usando protocolo uart por medio del puerto serial uart, comunicacion asincrona, el proyecto requiere que se lea un numero en binario tomado desde los switchs que trae la tarjeta y muestre el valor ingresado en formato decimal en el lcd 7 segmentos, adicional a eso que esta información sea transmitida via puerto uart al computador. los entregarles son el codigo hecho en verilog,( make file, archivos.v ) ademas de brindar una breve explicacion del trabajo realizado. hay un p...
Necesito para nuestro equipo de 15 ingenieros incorporar dos nuevos ingenieros con ilusión, cierta experiencia y conocimientos en VHDL/Verilog y microprocesadores. Es trabajo a tiempo completo y con estabilidad (2 años). Ubicación: Sevilla y Albacete. Uno en cada sitio.
Modificaciones y rutinas extras para- gestión de dispositivos procesado de imágenes video / foto reducción de tiempo de procesado Ubicación Tres Cantos, Madrid Conocimientos de FPGAs / VHDL un plus trabajo a realizar en Abril 2017
Controlar la velocidad de un motor mediante PID usando encoder, en lenguaje VHDL para la tarjeta Basys 2 Spartan 3.
Ascensor 4 pisos, mediante una targeta basys 2 en una spartan 3e
necesito realizar proyectos en la tarjeta Nexys 2 vhdl del fabricante que tiene el procesador spartan 3E de xilinx practicamente lo que busco es un manual tecnico de como descargar los softwares necesarios para el trabajo, describir paso a paso de como realizar un programa utilizando el puerto vga de la tarjeta , en concreto un programa completo basado VHDL que me permita con este programa piloto modificarlo para generar otros programas basados en el puerto VGA
Realiza un circuito básico de PWM donde el tiempo en alto pueda modificarse en pasos de 10%. Simula el circuito y comprueba su funcionamiento. Deben verse varias consignas, compronado que la anchura de la salida es la correcta. Para este apartado puedes realizar una compilación funcional. ? Cambiando el tipo de compilación a no-funcional, compila el diseño eligiendo el dispositivo FLEX10KRC240-2. Utiliza las herramientas de MaxPlusII para obtener la frecuencia máxima de trabajo a la que puede funcionar el sistema. Mirando la información que aparece en el report file (fichero .rpt), indica el porcentaje de recursos lógicos que ocupa tu diseño. ? Escribe los resultados en un documento y mándaselo al profesor, junto con un archivo...
Particular busca urgente programador para tarea REMUNERADA en vhdl (facililla). Se trata de una práctica de 3º de telecomunicaciones para entregar en 10 días. Texto tarea: Realiza un circuito básico de PWM donde el tiempo en alto pueda modificarse en pasos de 10%. Simula el circuito y comprueba su funcionamiento. Deben verse varias consignas, compronado que la anchura de la salida es la correcta. Para este apartado puedes realizar una compilación funcional. ● Cambiando el tipo de compilación a no-funcional, compila el diseño eligiendo el dispositivo FLEX10KRC240-2. Utiliza las herramientas de MaxPlusII para obtener la frecuencia máxima de trabajo a la que puede funcionar el sistema. Mirando la información que apar...
Soy de colombia Programar un juego llamado simon dice En VHDL y en el programa llamado Xilinx Simón dice Colores El juego Simón dice colores es un juego de memoria donde el jugador deberá seguir la secuencia de colores que “Simón” aleatoriamente va generando. cada uno asociado con un color (verde, amarillo, azul y rojo). Cada acierto de la secuencia completa de colores por parte del jugador incrementa el nivel y Simón agrega un nuevo color a la secuencia. El juego termina cuando el jugador se equivoque o cuando alcance el número máximo de niveles para los que fue diseñado el juego, el cual en ningún caso deberá ser menor a 32 niveles.
I'm looking for someone with experience in VHDL to help me create a testbench for an ual_core.vhd. This testbench would need to be completed within 1 week, and it is up to the freelancer’s discretion to determine the exact details. I am looking for someone with the knowledge and expertise to create a quality testbench to meet the timeline and deliver the results I'm expecting, and is able to understand french. Please reach out if you have the skills and experience needed to complete this task.
...to help with a project involving Xilinx FPGA development. I am using the Xilinx Zynq-7000 board and the main function of the board in my project is to process data. I need help with both hardware design and software development for this project. The qualified candidate should have significant expertise in hardware design and software development for FPGA systems. Excellent knowledge of C/C++ and VHDL for FPGA design/programming is also necessary. The candidate should be able to understand and utilize various types of FPGA peripherals and interfaces including, but not limited to, SPI, I2C, UART and Ethernet. Working knowledge of the Zynq-7000 series FPGA board and its associated software/tools (e.g. the Xilinx Vivado Design Suite) is also a requirement. Finally, the qualified cand...
I want to implement the Ethernet connection between FPGA board to PC. The deliverables are as follows - Verilog code to run on a Spartan 6 Board - (xc6slx100) - Simulation time diagrams (more details will be given to the winner) - The code should be able to transmit and receive data at 1000mbs.
I am looking for an experienced VHDL programmer to help with a complex project. The timeline for this project is within a week, so it will require an experienced programmer who is able to work very quickly. I have detailed requirements that need to be satisfied, and I will be expecting a high-quality result. The project is an advanced level project, so I need someone who is comfortable working with complex VHDL code. If you think you can complete this project in the timeline given, please message me!
Project Description: Can you help me with a mini spectrum analyzer using FPGA the results will be on a pc screen with GUI that the user can put markers on and change the resolution, to make a spectrum analyzer with FFT algorithm on FPGA Using UI the user can control the span a put markers. The user will be able to change parameters in a user interface. The ADC is the sampling. The FPGA is going to calculate the FFT. The all idea is to mini spectrum analyzer (the measurement device). Block chain 1. ADC for sampling 2. FPGA to calculate the FFT and sent it to the pc display
I am looking for a freelancer to help with hardware verification. Specifically, I would like someone to verify a VHDL model od SHA3 in SystemVerilog using the UVM (Universal Verification Methodology). This project will also require executing fewer than 10 verification test cases. I have semi-built UVM template to send.
Hi I am writing the code for UVM verification environment for the AMBA AHB. I have all the code but facing problems integrating it with errors. It's to be done in vivado or questasim. It's in system verilog language. I need it in 2 days. We could discuss the price based on the difficulty and time you have to give on this.
My experience with deploying Caffe networks on FPGA boards is intermediate. I have prior experience with the Lattice Radiant software so I am ready to use it for this project. My specific task or outcome I want to achieve with this deployment is Image Classification using the ICE40UP5K FPGA with the iCE40 UltraPlus Breakout Board and Lattice Radiant software.
My project is about FPGA programming for control systems. I'm using the Altera Cyclone V board and the preferred programming language is Verilog. This project requires someone with experience in FPGA programming and the design of embedded systems. The programmer should be able to develop design flows for FPGA devices, debug them and modify existing designs for better performance. The knowledge of hardware description languages such as VHDL and Verilog is crucial, as they will be used for implementation and testing of the designs. Additionally, some knowledge of microcontrollers and communication protocols will be required. The right person for this job should have strong problem-solving skills, excellent coding and debugging capabilities, and a deep understanding ...
I am in need of an experienced and professional digital circuit designer to undertake a project involving Verilog coding, RTL verification, and FPGA implementation. Specifically, I need the Verilog coding to be at the intermediate level and it must meet specific requirements. The scope of this project is just Verilog coding running though Xilinx Vivado IDE. The successful applicant must have a good understanding of design flows to be implemented in Verilog, including synthesis and simulation techniques, as well as a thorough knowledge of all aspects of Verilog coding and digital circuit design. Experience with RTL verification and FPGA implementation will also be beneficial for this role. Ultimately, I am seeking an individual who is able to accurately an...
Project Title: Altera DE0 Board Programming Assistance Description: I am seeking a freelancer who can provide programming assistance for my Altera DE0 board project. I require expertise in VHDL programming language and the ability to modify existing code as well as start from scratch. Skills and Experience: The ideal candidate for this project should have: - Proficiency in VHDL programming language - Experience with Altera DE0 board - Strong troubleshooting and debugging skills - Knowledge of hardware design consultation Specific requirements: - Provide programming assistance for the Altera DE0 board - Modify existing code and develop new code from scratch - Troubleshoot and debug any issues that arise during the programming process - Provide hardware design consultation a...
I am looking for a skilled programmer to work on the video processing project involving the GS2962 and GS2961 ICs. Programming Language: - Proficiency in VHDL programming language is required for the IC programming. Functionality: - The primary function of the programmed ICs should be video processing. Hardware Compatibility: - The IC programming should be compatible with specific hardware that I have specified. Ideal Skills and Experience: - Strong knowledge and experience in programming with VHDL language. - Expertise in video processing and working with ICs. - Familiarity with GS2962 and GS2961 ICs. - Ability to ensure compatibility with specified hardware. Please provide examples of previous projects related to video processing and IC programming when submittin...
I am looking for a skilled ARM embedded freelancer to assi...Purpose of the Embedded System: - Personal project Hardware and Software Requirements: - I have specific requirements Ideal Skills and Experience: • Good grasp of fundamentals in Electronics Engineering, • Knowledge of digital electronics, VLSI, microprocessor architecture is a plus • Interest and experience in digital design and verification • Good understanding of Assembly-level programming, Verilog/VHDL • Proficient in C/C++, and scripting languages - Strong knowledge and experience in ARM microcontroller programming - Proficiency in real-time operating system (RTOS) development - Expertise in embedded system design and implementation - Familiarity with the specific hardware and softw...
I am looking for a skilled VS code extension developer who can create a language support extension for VHDL/Tcl. The ideal candidate should have experience in developing VS code extensions and have a strong understanding of external tasks. Requirements: - Proficiency in developing VS code extensions - Familiarity with the VS code extension development process - Ability to create a language support extension We have a language support extension already, that support VHDL and Tcl programming language. we need support to add tasks to the extension, to call external scripts. more details in following communications
I am looking for an experienced Verilog FPGA specialist to develop a reliable and efficient code for me. I do not have a specific functionality in mind, but I do need the code to have a clock frequency of less than 100MHz and fewer than 10 inputs and outputs. I would also like to ensure that the code is reliable and bug-free. If you have the expertise and skill set to deliver a high-quality solution, please contact me. I look forward to hearing from you!
Task description. we have a fork of a VScode extension which we customized (modifying snippets and some minor modification) This should be extended, we want to create an extension to be used internally to the company by every FPGA designer the extension shall support VHDL and Tcl (snippets and language syntaxes files are there already) Add Tcl language support (, ) but we would like to add the capability to call external Tcl scripts, right clicking on a vhd file in the Explorer Tab
I am looking for a skilled VS code extension developer who can create a language support extension for VHDL/Tcl. The ideal candidate should have experience in developing VS code extensions and have a strong understanding of external tasks. Requirements: - Proficiency in developing VS code extensions - Familiarity with the VS code extension development process - Ability to create a language support extension We have a language support extension already, that support VHDL and Tcl programming language. we need support to add tasks to the extension, to call external scripts. more details in following communications
Project Description: Build Pulp Snitch Cluster for Xilinx FPGA Board I am looking for a skilled and experienced developer to build a Pulp Snitch Cluster for my Xilinx FPGA Board. The ideal candidate should have expertise in System Verilog programming and configuration. Requirements: - Create a project, so Pulp Snitch Cluster can be built for Xilinx FPGA Board (Kria 260) using command line - Strong knowledge and experience in System Verilog programming and configuration Skills and Experience: - Expertise in System Verilog programming and configuration - Familiarity with Xilinx FPGA Boards - Familiarity with Xilinx tools (Vivado, etc..)
Project Title: Familiarize with pulp-platform/snitch Description: I'm seeking the one who can make me familiarized with pulp-platform/snitch. As of the output I expect to have : Completed documentation, from which I ...other tools) 2. Have understanding of how to run unit tests for given modules/cores/clusters/whatever 3. Embed custom IP into a snitch cluster; connect it to the axi crossbar, make it configurable by one of the cpu's/external tool 4. Use xilinx simulator for the purpose of unit tests (as a bonus) Note: latest version of the pulp/snitch must be used Skills and Experience: - Experiense with system verilog/ verilator/ system c/ make/ python - Experience with pulp-platform/snitch - Strong understanding of hardware and software integration - Communication and ...
Hi Edgar G., We need a tcl script to create block design from VHDL, FSM representation with states and transitions (with conditions), and process interconnection. This will be needed for documantation of VHDL projects consider splitting the diagram in sub diagrams for very dense diagrams, where the readability will be compromised byt the vast number of blocks and connections. the output shall be in an editable format.
Online forum dissemination and flyers The goal of this task is to "disseminate" our products and solutions on the web example: lets suppose we have our "axi register vhdl generator" module which generates VHDL module and package, C header and function to read/write registers, and html documentation. All this automatically from a tcl script or a web interface We would need to search on the web (in forum for instances) people looking for that thing and reply, sending a message, with the link to our solution This should be done, possibly, automatically, to capture the message as soon as it is published and reply immediately (replying after 2 years is not good, though it is still valid as the link will still be present and someone might go to serach and ...
I am in need of an FPGA VHDL expert for a design and implementation project. Skills and experience required: - Expertise in FPGA VHDL design and implementation - Strong knowledge of digital design and verification - Proficiency in troubleshooting and debugging FPGA designs Successful freelancers should include their experience in their application, showcasing their past work and relevant projects they have worked on. The desired turnaround time for the project is 2-4 weeks.
Project Description: I am looking for an experienced FPGA developer to implement a PL UART communication module on a Zynq FPGA. The project requires the following skills and experience: - FPGA development experience, specifically with Zynq FPGAs - Knowledge of UART communication protocols - Proficiency in HDL programming languages such as Verilog or VHDL - Ability to implement custom baud rates for UART communication - Experience with interrupt handling in FPGA designs - Strong understanding of intermediate level communication requirements The main objectives of the project are: - Implementing a PL UART module on a Zynq FPGA - Supporting selectable baud rates for UART communication - Triggering an interrupt after a successful transmission - Ensuring reliable and efficient ...
I need an experienced programmer to write FPGA test code for an upcomi...using. As this project requires moderate complexity, it is essential that the person I choose has a sound knowledge and understanding of FPGA programming. The code I am looking for is interface testing code for Audio IC (Audio Codac Part No: ADAU1761) with FPGA. Problem Statement:- We have to test the Audio interface of our customized FPGA board(FPGA PART No: XC7K325T-2FFG676I), so we need a VHDL/Verilog code for Audio IN/Out. Means, when we give input from Mic in audio in, same will be transferred to Audio out which we will hear from speaker. If you think you have the qualifications, tools and knowledge necessary to craft the code, please do not hesitate to bid on the project. I loo...
I am looking for an expert in Verilog and FPGA development to help with a project involving a UART. The project requires the following: Data Transfer Rate: - The required data transfer rate for the UART is up to 115200 bps. FPGA Board: - The specific FPGA board being used is Xilinx. Functionality: - The desired functionality of the UART is basic data transfer. Ideal Skills and Experience: - Strong knowledge and experience in Verilog and FPGA development. - Familiarity with Xilinx FPGA boards. - Experience in implementing UART functionality. - Understanding of basic data transfer protocols and techniques. If you have the expertise and skills required for this project, please submit your proposal.
The states are Idle state, Authentication state, menu state, withdraw state, deposit state, mini statement state, extra states can be added, if necessary. Moore implementation would be ideal as it is easy to implement, the model should be able to perform contain the following: 1)Withdraw 2)Deposit 3) Mini statement (up to 4 transactions) 4)Block the account for 24hrs if an incorrect pin is entered 3 times It is preferable if the Implementation of the STATES is done in different submodules and overall flow is controlled by the Main module containing the FSM. I/O utilization is recommended to be kept at minimum. Simulation with testbench simulation, Synthesis and Implementation is desired. Assume required power constraints and timing constraints for the model to work. Assume any other speci...