I need someone to do the coding in Vivado for a very simple project. This project involves a Xilinx CPU and Analog Devices AD9362. Send and receive a simple sinusoidal waveform. For more information send me your CV. I will test the code on the board and if works I will pay the salary. Thanks,
I need to get 5 miliseconds data, each time I press a button B1. Data needs to be saved one after another in the DDR3 memory. When I press another button B2, the data from DDR3 must be sent to a CP2102 TTL-USB adapter at 115200 baud rate, so I can donwload data to PC. The aquisition speed is 125Msps, at 14bit.
Need someone familiar with Verilog, C, and logical circuits (Karnaugh maps, etc). The complete details will be provided in the chat.
Hello, I want to design a verilog module where input is AXI Stream and output can be either RAW10 or RAW12 pixel data as per input selection. I have my own code for MIPI RAW8. Need to add RAW10 and RAW12 functionality.
Implementation of n bit ALU using Novel Adiabatic Logic using cadence virtuoso tools in 45nm technology and verification of its operation. Implementation of n bit ALU using CMOS Logic using cadence virtuoso tools in 45nm technology and verify its operation. Analyze and Compare the both in for different parameters like power, delay, power delay product, area,vdd, and operating frequency etc. Show t...
Use xc7k420t for mining, beaglebone as mining management, and use uart to manage 6 420t chips for parallel computing. Calculate some current small currencies for blockchain research, such as ckb, trb, kda，hns and so.
Title is to optimize the PID controller and Lag Lead compensator for machine tool i. to optimize the parameter of PID and Lag-Lead controller by using PSO technique ii. to stimulate the controller and compare the tracking error and RMSE of both controller for the machine tool.