CMOS-VLSI on Virtuoso Cadence -- 2
$30-250 USD
Pagado a la entrega
c Integrated Circuit (ASIC) implementation of an N x
N array multiplier. The ASIC will be fabricated in AMI 0.5 m CMOS technology available through
MOSIS.
Nº del proyecto: #15744950
Sobre el proyecto
1 freelancer está ofertando el promedio de $231 para este trabajo
Hi, I do have cadence virtuoso. I can provide you layout design of your project if you have schematic. If you want layout can be provided in 130/180 nm TSMC node LVS,DRC will be cleaned Thanks...