I need a coder that is proficient in VHDL coding and Usage of FPGA board(BASYS3)

Dear sir I have more than 10 years experience in digital design using FPGA please check my profile also please message me so that we can discuss Best regards

A highly-skilled FPGA engineer with 7+ years experience and hundreds of FPGA/Verilog/VHDL projects using Xilinx/Altera FPGA Design Tools and Digital Logic Design using LogiSim/CEDAR. Founder of FPGA4student. Expertise: FPGA, Verilog, VHDL, Xilinx ISE, Vivado, Altera Quartus, Modelsim, Logisim, CEDAR, MIPS Assembly, PLP Tools, Qtspim, MARS, PCB Design, Altium Designer, OrCAD, PSpice, Proteus, Arduino, CMOS VLSI Design, Cadence Virtuoso, Layout XL, Digital IC Design from RTL to GDSII, Analog IC Design. - Featured FPGA projects: + Video/Image Processing on FPGA: FPGA/Verilog/VHDL Implementation of Gesture Recognition, Fingerprint Identification, Image Compression in Wavelet Domain using DWT and SPIHT, Image Enhancements including Noise Filtering. + Fixed-point and Floating Point FPGA projects in Verilog/VHDL + AES, SHA 128, 192, 256 Implementations on FPGA + Single/Multicycle/Pipelined RISC/MIPS Processors in Verilog/VHDL/Logisim + Games on FPGA and many other FPGA projects

Hi, I hope you are doing well and enjoying digital design. I believe implementing a design right form modeling until verifying it on an FPGA is always a very special experience. Throughout my 2+ years of experience in the field, I had the joy of designing and implementing a part of LTE's physical layer right from the Matlab model, through RTL coding, simulations, and back-end stages. I also built many other designs such as a MIPS processor design, Can satellite, and a UART transmitter and receiver. All my designs were verified successfully on either Xilinx's Spartan S6, S3, or Altera's Cyclone V FPGA. The process of building some RTL design differs according to the final destination of the project. For instance, a design for ASIC tape-out will have other methodologies of debugging and verification than if it's for FPGA. Subsequently, I would like to know which methodology of testing you would prefer me to adopt, simulations or UVM environments. It is up to you really. I am fine with both. I would love to hear your thoughts and requirements for the delivery as well. I wish you get the best out of this project. - Eslam

hi, is your project has due date? I am interested.

VLSI xilinx

I am interested in your project and glad to offer you my help