fpga video processing pipeline. - 12/01/2023 17:14 EST

accept digital RGB input (24bit + HS VS DE) in one resolution, output digital RGB output (24bit + HS VS DE) in another resolution. Features required : 1. optional de-interlacer (switchable motion adaptive and weave). 2. optional frame rate converter (50->60hz or 60->50hz) 3. scaler with following features 3.a. switchable aspect ratio 4:3 or 16:9 3.b. parametrized integer upscalling rate (1x input, 2x input, 3x input) - no interpolation 3.c. switchable upscaling filters (like hq2x) 4. output from scaler is passed through optional scaline generator, where scanline parameters are passed as input wires : scanline color, scanline thickness, scanline interval 5. output is overlayed by the bitmap OSD with the same resolution as output format Requirements : aside from the DDR memory interface, or PLL no vendor or encrypted IP blocks can be used, for example no Altera/Intel video pipeline. Everything must be in written verilog source code. Must include verilog testbench that will accept input picture(in any format) and produce resulting picture(in any format). suggested pipeline i/o ports: Sysclk, [23:0] RGBin, HSin,VSin,DEin, Clkin [23:0] RGBout, HSout, VSout, DEout, Clkout [31:0] parameters[0:...] (whatever count is required). all needed memory interfaces signals to the memory multiplexer. Any dev board and any FPGA device can be used for testing it on. It is essential that the potential developer will provide the samples (with code fragments) of previous experience. More than 3 years of Verliog/ HDL experience is a must.