Solving FPGA output module

Cerrado Publicado hace 5 años Pagado a la entrega
Cerrado Pagado a la entrega

1. Design platform: VIVADO 18.2

2. Chip: xcz7020CLG484-1

3. language: Verilog

4. Input is all lvds, fclk is frame clockwise, DCLK is data clock, DDR mode

Data receives 16 pairs of ADC data. A pair of LVDS DATA inputs 2 channels of ADC data. FCLK is channel A data when it is high and channel B data when it is low. Output data with 32 channel bit width of 12

Arduino Electrónica FPGA Microcontrolador Verilog / VHDL

Nº del proyecto: #18284036

Sobre el proyecto

4 propuestas Proyecto remoto Activo hace 5 años

4 freelancers están ofertando un promedio de $182 por este trabajo

EslamElGeddawy

Hi, I hope you are doing well and enjoying digital design. Throughout my 2+ years of experience in the field, I had the joy of designing and implementing a part of LTE's physical layer right from the Matlab model, Más

$140 USD en 4 días
(7 comentarios)
4.2
supersuntech

Hello, I have 3 years of experience in internet of things. I am able to control appliances via internet using cloud or Bluetooth. Also able to work on raspberry Pi, Arduino, esp and other hardware programming. Más

$200 USD en 5 días
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0.0
waqarahmed190

I have rich expierience with fpga interfaces using adc, dac, spi , emif , asp etc etc. Your ZYNQ device have a internal ADC and can support external also.

$222 USD en 4 días
(0 comentarios)
0.0
abehin98en1992

I have experience in high speed serial ADC data acquisition using SERDES/selectio in ZynQ FPGA. Let's have a chat for more details.

$166 USD en 5 días
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0.0