Imagen de perfil de punamsengupta
Bandera de India Delhi, India
Miembro desde 2 de noviembre de 2015
1 Recomendaciones


En línea Desconectado
Total experience of 7 years into Semiconductor and EDA Industry. Throughout experience in module level RTL coding , verification of ASIC designs and VIP Development. 4+ years of experience in constrained random based Functional verification in front end ASIC flow. Well conversed with verification methodologies such as OVM, UVM for more effective and re-usable test bench component knowledge and familiarity of Functional coverage concepts and System Verilog with APB, I2C, OCP, IOSF, JTAG and USB protocols. Assets as a freelancer: 1. Highly motivated to work on my own. 2. Effective and detailed Communication skill. 3. Ability to learn new technology rapidly, work flexibly and take new initiatives. Technical Exposure: 1. Good expertise in C++ programming language. 2. Very Good expertise in verilog and system verilog languages. 3. Good knowledge of Perl scripting. 4. Good expertise in OVM and UVM methodologies.
$15 USD / hora
13 comentarios
  • 85%Trabajos finalizados
  • 100%Dentro del Presupuesto
  • 58%A tiempo
  • 20%Tasa de recontratación


Comentarios recientes


Senior Verification Engineer-I

Apr 2013 - Apr 2015 (2 years)

Project : USB 2.0 Block level verification.

R&D Engineer-II

Jul 2012 - Mar 2013 (8 months)

Project : AMBA APB VIP Development .

Senior Project Engineer

Jun 2008 - Jun 2012 (4 years)

Project 1 : Modular PHY DFX Verification. Project 2: Verification of IOSF2OCP Bridge.


M.Tech (VLSI)

2006 - 2008 (2 years)

B.E (Instrumentation and control engineering)

2001 - 2005 (4 years)


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