Imagen de perfil de punamsengupta
Bandera de India Delhi, India
Miembro desde November, 2015
1 Recomendaciones


En línea Desconectado
Total experience of 7 years into Semiconductor and EDA Industry. Throughout experience in module level RTL coding , verification of ASIC designs and VIP Development. 4+ years of experience in constrained random based Functional verification in front end ASIC flow. Well conversed with verification methodologies such as OVM, UVM for more effective and re-usable test bench component knowledge and familiarity of Functional coverage concepts and System Verilog with APB, I2C, OCP, IOSF, JTAG and USB protocols. Assets as a freelancer: 1. Highly motivated to work on my own. 2. Effective and detailed Communication skill. 3. Ability to learn new technology rapidly, work flexibly and take new initiatives. Technical Exposure: 1. Good expertise in C++ programming language. 2. Very Good expertise in verilog and system verilog languages. 3. Good knowledge of Perl scripting. 4. Good expertise in OVM and UVM methodologies.
$15 USD/hr
12 comentarios
  • 92%Trabajos finalizados
  • 100%Dentro del presupuesto
  • 59%A tiempo
  • 22%Tasa de recontratación


Comentarios recientes

  • imagen de jonathanrossy Writing a verification plan for a Design under test in system verilog -- Project for punamsengupta $60.00 USD

    “My go-to freelancer for anything related to VLSI projects.I had an urgent requirement on this and she delivered this in few hours which is amazing. She is an experienced person and technically very sound. She always delivers before time and makes sure everything is as per requirements and always exceeds the expectations. Will hire her again .”

  • imagen de myworldvw FPGA Implementation $30.00 USD

    “The project is not completed according to the dispute”

  • imagen de shivratan84 Project on VeriLog $100.00 AUD

    “She is a good asset.”

  • imagen de aswinvijayavarma Verilog Implementation of Pipelined Execution of Windowed Image Computations $350.00 USD

    “Punam is very well versed with Verilog coding. She has a good understanding of digital logic as well. She delivered a very quality code to me. My suggestions for code changes were very well taken. She took extra effort on some days to debug the code to implement exactly what I wanted. I would recommend anybody to hire Punam, for the knowledge she has in digital design.”

  • imagen de sunilkumart19 Project for punamsengupta ₹15000.00 INR

    “awesome experience working with.”

  • imagen de jonathanrossy Simple queston regarding Virtual memory and the calculation of page size $20.00 USD

    “"Thorough detailed solution to the problem. Very knowledgeable freelancer. I have been hiring her for all my recent projects. Will hire her again"”


Senior Verification Engineer-I

Apr 2013 - Apr 2015 (2 years)

Project : USB 2.0 Block level verification.

R&D Engineer-II

Jul 2012 - Mar 2013 (8 months)

Project : AMBA APB VIP Development .

Senior Project Engineer

Jun 2008 - Jun 2012 (4 years)

Project 1 : Modular PHY DFX Verification. Project 2: Verification of IOSF2OCP Bridge.


M.Tech (VLSI)

2006 - 2008 (2 years)

B.E (Instrumentation and control engineering)

2001 - 2005 (4 years)


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