Dear sir,
I am a digital design engineer expert in FPGA and ASIC design flows using Verilog and VHDL programming. Also, I am experienced with Vivado, ISE, Vivado IPs, SDK, Quartus, Design Compiler, IC Compiler and others.
I have done AES on FPGA using Vivado HLS.
https://www.freelancer.com/u/IslamAdam998/portfolio/AES-128-Encryption-Decryption-9028084?w=f&ngsw-bypass=
Please contact me to discuss more about this project.
Kindest regards.